Compared with silicon (Si), silicon carbide (SiC) has properties which include an insulation breakdown electric field that is an order of magnitude greater, a band gap that is 3 times greater and a thermal conductivity that is about 3 times higher, and therefore holds considerable promise for applications to power devices, high-frequency devices, and high-temperature operation devices and the like. As a result, in recent years, SiC substrates are increasingly being used as substrates of semiconductor devices.
The SiC substrates described above are produced, for example, from bulk single crystal ingots of SiC prepared by a sublimation method or the like. Usually, the outer periphery of the ingot is ground and processed into a cylindrical shape, a wire saw or the like is then used to slice the cylindrical shape into circular discs, and the external periphery is then chamfered to a prescribed diameter to obtain the substrate. Moreover, the surfaces of the circular disc-shaped SiC substrate are subjected to a grinding treatment using a mechanical grinding method to remove unevenness and achieve parallelism of the surfaces. Subsequently, one surface or both surfaces of the substrate are provided with a mirror finish by subjecting the surface(s) to mechanochemical polishing such as CMP (Chemical Mechanical Polishing). This type of grinding and polishing of the SiC substrate is performed for purposes such as removing undulations and process distortions generated by the slicing process, and planarizing the surface of the SiC substrate.
The type of CMP method mentioned above is a polishing method that has both a chemical action and a mechanical action, and therefore a planar surface can be obtained in a stable manner, without damaging the SiC substrate. As a result, CMP methods are widely employed in production processes for SiC semiconductor devices and the like, as a method for planarizing either roughness or undulations that have been generated on the surface of the SiC substrate, or planarizing unevenness due to wiring or the like on a wafer obtained by stacking an epitaxial layer on the surface of the SiC substrate.
SiC (epitaxial) wafers obtained using an SiC substrate are usually produced by using a chemical vapor deposition (CVD) method to grow an SiC epitaxial film (epitaxial layer) that functions as an active region of the SiC semiconductor device on an SiC substrate obtained using the procedure outlined above. On the other hand, if an SiC substrate that has been sliced from an SiC single crystal ingot is used in an unmodified state, with unevenness or undulations on the substrate surface, then the surface of the epitaxial layer deposited on the surface of the SiC substrate may sometimes also develop unevenness or the like. Then, when producing an SiC wafer by growing an SiC epitaxial layer on an SiC substrate, the surface of the SiC substrate should first be polished using a CMP method, before the SiC epitaxial layer is grown on the surface of the substrate. Following growth of the SiC epitaxial layer, a roughness removal treatment or planarization treatment for the surface of the SiC wafer is conducted by performing a grinding treatment using a mechanical grinding method and a finishing polishing treatment using a CMP method in a similar manner to that described above.
If semiconductor elements such as transistors or diodes are formed on the surface of the epitaxial layer on the SiC substrate to produce a semiconductor device while undulations or process distortions still remain on the substrate surface, then it becomes difficult to obtain the types of electrical characteristics that are expected based on the superior physical properties inherent to the SiC. Accordingly, the aforementioned type of planarization treatment used for the surface of an SiC substrate containing an epitaxial layer is an extremely important process.
Generally, a mechanical polishing method such as lap polishing is effective as a treatment for removing undulations or process distortions from the surface of an SiC substrate. In terms of surface planarization, polishing using diamond having a particle size of not more than 1 μm, or grinding using a whetstone having a high grit size of at least #10,000 is effective. Moreover, in terms of finishing processing on an SiC substrate surface prior to growing an SiC epitaxial film (epitaxial layer), or finishing processing on a wafer following growth of an SIC epitaxial layer, a polishing process using a CMP method is generally performed to reduce the surface roughness Ra to a value of less than 0.1 μm.
A method for polishing the surface of an SiC substrate using a CMP method is described below using FIG. 6.
As illustrated in FIG. 6, an SiC substrate 100 that has been sliced from an ingot and then subjected to surface grinding using a mechanical grinding method is mounted on a rotatable SiC substrate support portion 201 provided in a CMP polishing apparatus 200. Then, the SiC substrate 100 is pressed against a polishing pad 202a affixed to the surface of a rotating surface plate 202. Further, at the same time, the SiC substrate support portion 201 is rotated while a slurry 204 is supplied from a slurry tube 203 to the interface between the polishing pad 202a and the SiC substrate 100. As a result, the polishing surface (upper surface) 100a of the SiC substrate 100 can be polished.
Generally, when an epitaxial layer is deposited on the Si surface that represents the deposition surface of the SiC substrate, surface roughness that develops on the surface of the layer is a problem, and particularly when the thickness of the epitaxial layer is increased, the roughness of the layer surface becomes quite noticeable. This is mainly due to roughness that occurs as a result of step bunching when the epitaxial layer is grown thickly.
For example, as illustrated in FIG. 5(a), prior to deposition of the epitaxial layer, because the SiC substrate has been subjected to polishing using a CMP method, almost no surface roughness is visible, and even in an evaluation using AFM imaging, almost no unevenness or defects can be detected. However, as illustrated in FIG. 5(b), if a thick epitaxial layer of about 30 μm is deposited on the SiC substrate, then a state of roughness develops across the entire layer surface, step bunching can also be detected in the AFM evaluation, and large epitaxial defects in the order of several tens of μm also tend to occur readily.
On the other hand, roughness that occurs due to the type of step bunching described above has a height of about 0.01 μm in the layer thickness direction. Consequently, as illustrated in FIG. 5(c), by subjecting the surface of the epitaxial layer on which roughness has developed to CMP processing using a removal amount of about 1 μm, the roughness due to step bunching and the like can be removed. In other words, provided the roughness on the epitaxial layer surface can be removed using the type of method described above, a large layer thickness that is suitable as the epitaxial layer for a high-pressure resistant device can be maintained, and an SIC epitaxial substrate having minimal roughness can be formed. This offers the advantage that devices having excellent element characteristics can be produced in subsequent device formation steps. In other words, finish polishing of the epitaxial layer surface is an extremely important process.
Examples of the aforementioned type of method for polishing an SiC substrate surface using a CMP method with the purpose of removing the surface roughness from an epitaxial layer deposited on the SiC substrate include the type of method proposed in Patent Document 1. Patent Document 1 discloses a method in which a plurality of SiC substrates are mounted on a rotating table, and CMP polishing is then performed using a batch treatment.
Patent Document 2 discloses a method for forming a channel region in a production process for a semiconductor device, wherein the channel region is formed by polishing and planarizing an epitaxial layer.